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description designed to provide the motor driver and power supply requirements for printers and office automation equipment. this integrated power ic incorporates two high current, high performance, full bridge outputs, capable of 1.5 a at 50 v. additionally two power supply rails are provided for microprocessor or dsp supplies. a switching buck regulator steps the supply down to a low voltage output that is adjustable from 3.3 to 5 v. this voltage can be used to supply external 5 v rails, it also feeds back into the part and supplies the integrated linear regulator which is adjustable from 1 to 2.5 v. the A3998 serial port provides flexible configuration for the dual full bridge motor driver. two full bridges can be programmed to control one stepper motor or two dc motors. both bridges have integrated fixed off-time pwm control with programmable decay mode selection. the A3998 is supplied in a low profile, 32-contact qfn, 5 5 mm, 0.90 mm nominal height, with exposed thermal pad (suffix et). the package is lead (pb) free with 100% matte-tin leadframe plating. A3998-ds features and benefits ? 3.3/5 v switching regulator ? 1 to 2.5 v configurable linear regulator output ? dual dmos full bridge: drive two dc motors or a single stepper motor ? 1.5 a, 50 v output rating per bridge ? 4-bit microstepping capability ? serial port control ? configurable mixed, fast, and slow current decay ? synchronous rectification for low power dissipation ? internal uvlo and thermal shutdown circuitry ? crossover-current protection ? ocp protection dual dmos full bridge motor driver with serial port control and dual regulators package: 32-contact qfn (suffix et) approximate size A3998 functional block diagram switcher pw m control charge pump system control full bridge 1 gate supply sense 1 out1a out1b vbb cp1 cp2 vcp 0. 1 f 42 v full bridge 2 serial port controller vbb fb1 sw1 data clk stb out2a out2b sense 2 enb2 enb1 vref clk vin fb2 csn ldo 3. 3 to 5 v 1a clk gnd vbb monitor pmon fb1 sleepn gnd vout2 vout1 vout1 1 to 2. 5 v 500 ma cout2 10 f vreg gnd gd/vout2 vreg to vreg q1 0.1 f 0.22 f d/a buffer control logic pwm control full bridge 2 pwm control full bridge 1 d/a vbb rst vbb frst 100 ms por l1 d1 r1 r2 cout1 220 f r cl2 r3 r4 rs1 rs2 220 f 0. 22 f c pad
dual dmos full bridge motor driver with serial port control and dual regulators A3998 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating unit load supply voltage v bb 50 v output current i out motor, dc 1.5 a pulsed, t w < 1 s6a sense voltage v sense dc 0.52 v t w < 1 s 2.5 v sw1 pin voltage v sw ?1 to 50 v logic pins voltage range v io ?0.3 to 5.5 v vin pin voltage v in ?0.3 to 6 v fb pins voltage range v fb ?0.3 to 5.5 v vref pin voltage range v ref ?0.3 to 5.5 v pmon, rst pins voltage range v rst ?0.3 to 5.5 v vreg pin voltage range v reg ?0.3 to 8 v operating ambient temperature t a s temperature range ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number packing* A3998settr-t 1500 pieces per 7-in. reel *contact allegro ? for additional packing options thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja 4-layer pcb based on jedec standard 30 oc/w estimated, on 2-layer pcb with 1 in. 2 of copper area each side 55 oc/w *additional thermal information available on the allegro website table of contents specifications 2 pin-out diagram and terminal list 2 thermal characteristics terminal list 3 electrical characteristics 4 functional description 7 voltage regulators 7 switching regulator 7 linear regulator 8 serial port 8 serial port writing 8 configuration register 9 motor driver 9 full bridge output current regulation 9 fixed off-time 9 pwm control mode 9 phase control 10 enable logic 10 fast decay time 10 pwm blank timer 10 synchronous rectification 10 protection 11 power-on reset 11 application information 16 pcb layout 16 switcher 16 motor driver 16 thermal considerations 16 switching regulator component selection 16 package outline drawing 19
dual dmos full bridge motor driver with serial port control and dual regulators A3998 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram terminal list table number name function number name function 1,13,32 gnd ground 18 sw1 dc to dc switch output 2 frst control logic input 19 cp1 charge pump capacitor terminal 3 sleepn control logic input, active low 20 cp2 charge pump capacitor terminal 4 clk control logic input 21 vcp reservoir capacitor terminal 5 data control logic input 22 nc no connect 6 stb control logic input 23 vreg gate supply 7 enb1 control logic input 24 csn current sense/reg select 8 enb2 control logic input 25 vin logic supply/ ldo supply 9 out2b dmos full bridge 2, output b 26 gd/vout2 gate drive output / vout2 10, 16 vbb motor and switcher supply voltage 27 fb2 feedback for vout2 11 out2a dmos full bridge 2, output a 28 fb1 feedback for vout1 12 sense2 sense resistor terminal, bridge 2 29 vref analog input 14 sense1 sense resistor terminal, bridge 1 30 rstn reset flag output 15 out1a dmos full bridge 1, output a 31 pmon power monitor flag output 17 out1b dmos full bridge 1, output b ? pad exposed thermal pad pad 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 gnd pmon rstn vref fb1 fb2 gd/vout2 vin out2b vbb out2a sense2 gnd sense1 out1a vbb csn vreg nc vcp cp2 cp1 sw1 out1b gnd frst sleepn clk data stb enb1 enb2
dual dmos full bridge motor driver with serial port control and dual regulators A3998 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1,2 valid at t j = 25c, v bb = 50 v; unless otherwise specified characteristics symbol test conditions min. typ. 3 max. unit load supply voltage range v bb operating 9 ? 50 v bridge output on-resistance r ds(on)rg source driver, i out = ?1.5 a ? 0.5 ? sink driver, i out = 1.5 a ? 0.5 ? vbb pins supply current i bb v reg regulated, i out = 0 ma, outputs on, pwm = 50 khz, duty cycle = 50% ? 5 10 ma i bbs standby mode, regulator active ? ? 5 ma vin pin supply current i in ? 5 8 ma control logic logic inputs voltage range v io operating 3 ? 5.5 v logic input voltage v io(1) v dd 0.55 ? ? v v io(0) ? ? v dd 0.27 v logic pins input current (except enb1,enb2, frst pins) i io v in = 0 to 5 v ?20 <1.0 20 a enb1,enb2, frst pins input current i io(1) v in = 3.3 v ? 66 100 a i io(0) v in = 0.8 v ? 16 40 a input hysteresis v iohys 200 ? 700 mv propagation delay time t pd pwm change to source on 350 550 1000 ns pwm change to source off 35 ? 250 ns pwm change to sink on 350 550 1000 ns pwm change to sink off 35 ? 250 ns crossover delay t cod 300 425 1000 ns supply monitor reset timer t por 70 100 130 ms rstn and pmon pins output voltage v rst i out = 1 ma ? ? 0.5 v rstn and pmon pins output leakage current i leakage v out = 5 v ? ? 1 a power monitor threshold v pm(th) pmon pin, v bb falling 12 13 14 v power monitor hysteresis v pmhys ? 2 ? v protection circuits vin pin uvlo threshold v inuv(th) v in rising ? 2.8 3 v vin pin uvlo hysteresis v inuvhys ? 100 ? mv vbb pins uvlo threshold v bbuv(th) v bb rising 6.6 7.1 7.6 v vbb pins uvlo hysteresis v bbuvhys 0.7 0.9 1.1 v fb1 pin uvlo threshold v fbuv(th) v fb falling 698 735 772 mv fb1 pin uvlo hysteresis v fbuvhys ? 100 ? mv thermal shutdown temperature t jsd 155 165 175 c thermal shutdown hysteresis t jsdhys ? 20 ? c continued on the next page?
dual dmos full bridge motor driver with serial port control and dual regulators A3998 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dc to dc converter feedback voltage regulation 4 v fb1 does not include cycle skipping mode (v = 9 to 50 v, i = 100 ma to 1 a) 0.98 1 1.02 v cycle skipping mode 0.95 1 1.05 v feedback input bias current i fb1 ?400 ? 100 na soft start duration t ss v bb = 9 v 5 10 15 ms current limit i clreg v fb > 400 mv 1.5 ? 2.7 a i clfb v fb < 400 mv .5 ? 1.2 a fixed off-time t off v out ?4 ? s buck switch on-resistance r ds(on)sw i = 1 a, t j = 25c ? 0.6 ? low drop-out regulator feedback voltage v fb2 i = 0 to 500 ma .98 1 1.02 v internal current limit i cl2 csn connected to vreg 525 ? 750 ma external current limit threshold v cl2 csn connected to sense resistor 180 200 220 mv vin pin voltage range v in v out +0.6 ? 5.5 v control circuit vref pin input voltage range v refrng operating 0.0 ? 2.6 v reference input current i ref v ref = 2.0, v bb = 0 to 50 v ? ? 1 a transconductance error 5 gm err v ref = 2.0, dac = 15 ?4 ? 4 % v ref = 2.0, dac = 3 ?10 ? 10 % internal oscillator frequency f osc 3.4 4 4.6 mhz 1 negative current is defined as coming out of (sourcing) the specified device pin. 2 specified limits are tested at a single temperature and assured over the range 0c to 125c by design and characterization. 3 typical data is for design information only. 4 average value of v out relative to target. 5 gm err =[(v ref current_ratio / 5) ? v sense ] / (v ref current_ratio / 5). electrical characteristics 1,2 (continued) valid at t j = 25c, v bb = 50 v; unless otherwise specified characteristics symbol test conditions min. typ. 3 max. unit
dual dmos full bridge motor driver with serial port control and dual regulators A3998 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com v outxa i outx i ocp outputs high-z v enbx t ocp t ocp ocp fault latch ocp delay motor short motor driver outputs disabled and serial port reset normal dc motor capacitance sleepn ocp fault latch clears at sleepn edge overcurrent protection (ocp) timing diagram rst function timing with frst input normal power-up timing diagram frst rst t por v bb charge pump ok (internal) v out1 rst pmon v out2 t ss t por
dual dmos full bridge motor driver with serial port control and dual regulators A3998 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description voltage regulators switching regulator an adjustable fixed off-time, peak current controlled buck regulator is used to provide external voltage to microprocessors or dsps. the switcher output is fed back into the device and provides low voltage logic supply for the ic, improving overall efficiency. the regulator can operate in both continuous and discontinuous modes. an internal blanking circuit filters out tran- sients due to the reverse recovery of the external clamp diode. the switching regulator fixed off-time of approximately 4 s is appropriate for the v out1 range from 3.3 to 5 v. light load regulation the switching regulator enters cycle skipping mode at light load conditions to maintain reasonable voltage regulation. as the output current decreases, there remains some energy that is stored during the power switch minimum on-time. the stored energy is transferred to the output capaci- tor and the output voltage begins to increase. to prevent energy in the inductor from pumping the supply voltage up, the A3998 can skip pwm cycles. cycle skipping mode can be activated any time there is discontinuous current in the inductor. soft start an internal ramp generator and counter allow the out- put to ramp-up slowly. this limits the maximum demand on the external power supply by controlling the inrush current required to charge the external capacitor and any dc load at start-up. internally, the ramp is set to 10 ms nominal rise time. shorted load the regulator incorporates an overcurrent limit to handle shorted load conditions at the regulator output. for low output voltages at power-up, and in the case of a short, the off-time is extended to prevent loss of control of the current limit due to the minimum on-time of the switcher. the overcurrent limit has a foldback feature to reduce the current limit when the output is overloaded (see figure 2). the voltage at the feedback pin (fb) is monitored to determine which current limit level to use. as the feedback voltage rises above approxi- mately 400 mv, the foldback circuit is disabled. t off + - 1v switch pwm control +- comp vcp i peak i demand clamp error 220 f/35 v soft start ramp generation clock counter gate reg internal oscillator esr monitor v bb uvlo enable tsd enable vbb vcp fb1 sw1 r1 l1 d1 r2 vout1 cout1 or figure 1. implementation of switcher circuit; see table 3 for external component specifications.
dual dmos full bridge motor driver with serial port control and dual regulators A3998 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com linear regulator an adjustable voltage rail from 1 to 2.5 v is integrated into the device. the switcher output is fed back into the device through the vin pin and supplies the integrated linear pass element. to reduce power dissipation in the A3998, the linear regulator can be configured to drive the gate of an external n-channel fet. using the external fet significantly reduces power dissipation in the ic and can allow the device to operate in high ambient temperature environments. the regulator has two configurations: internal mode and external mode. external mode is used to minimize power dissipation. in external mode current is limited by selection of the sense resistor, rcl. internal mode is selected by connecting pin csn to the vreg pin. both internal and external configurations are current limited. internal configuration when the internal pass element is con- figured the internal current limit is fixed at i cl2 . the regulator has overcurrent protection with foldback. figure 3 shows the i?v characteristic of the linear regulator. external configuration when the external pass element is configured the current is adjustable by selecting the value of a current limit resistor r cl2 . when the voltage across the resistor equals v cl2 the regulator enters current limit and will fold back according to the waveform shown in figure 3. to calculate the current limit use the formula below: v cl2 / i lim = r cl (1) where i lim is the target current limit. serial port serial port writing the serial port is accessed for writing only, using the stb (strobe), clk (clock), data and sleepn pins. addressing consists of word selection bits (d15:d14) followed by the bit values for each parameter in the word. timing requirements are shown in figure 4. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 vout2 voltage (v) vout2 current (a) v vout2 = 1.8 v v vout2 = 1.5 v v vout2 = 1.0 v v in = 5 v figure 3. linear current limit with foldback figure 2. switcher current limit with foldback 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.0 0.5 1.0 1.5 2.0 2.5 vout1 voltage (v) vout1 current (a) v vout1 = 5 v v vout1 = 3.3 v v in = 42 v
dual dmos full bridge motor driver with serial port control and dual regulators A3998 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com configuration register a configuration register supporting four 16-bit words can be set using the serial port. the configuration register is volatile memory accessed through the serial port. the bit descriptions are shown in table 1. at a power-on reset (por), the bits are set to their default values, all zeros with the exception of the msb of the fixed off-time param- eters, which are set to one. motor driver full bridge output current regulation maximum load current is regulated by an internal pwm mode, fixed off-time current control circuit. when the outputs of the dmos full bridges are turned on, current increases in the motor winding until it reaches a value given by: i trip = v ref current ratio / (5 r s ) (2) where r s is the value of the sense resistor rs, and the current ratio is as shown in table 2. at the trip point, the sense comparator resets the source enable latch, turning off the source driver. at this point, load inductance causes the current to recirculate for the serial port programmed fixed off-time period. the current path during recirculation is determined by the configuration of slow/mixed decay mode and the synchronous rectification control bits. fixed off-time the pwm timer is programmable via the serial port to provide fixed off-time pwm signals to the A3998 internal control block. five bits (word 0/1, d6:d2) are available for each full bridge to adjust the fixed off-time, t off , when internal pwm current control mode is selected. the off-time is defined by the following equation: t off = (1 + n ) t osc 8 ? t osc (3) where n is the word value, from 0 to 31, and t osc is the period of the internal oscillator. for example, given the internal oscillator frequency, f osc , of 4 mhz (typ) (t osc = 250 ns), the fixed off-time is adjustable from 2 to 64 s in increments of 2 s. pwm control mode the selection of internal or external pwm control mode for each full bridge is made in the configuration register. ? selection of internal control mode (word 2, d0 and d7) sets the internal pwm decay mode (mixed or slow), and allows the configuration of fixed off-time and fast decay time. in mixed decay mode, during the first portion of the off-time period, the A3998 operates in fast decay mode, until the fast decay time count is reached. the rest of the fixed off-time pe- riod the A3998 operates in slow decay mode. if the fast decay time duration is longer than the fixed off-time duration, the device effectively operates in fast decay mode throughout the period. ? selection of external control mode (word 2, d1 and d8) sets the external pwm decay mode (fast or slow). in this mode, a chopping signal on the enable pins (enbx) are used to provide external pwm current control. a. minimum data setup time 15 ns b. minimum data hold time 10 ns c. minimum setup strobe to clock rising edge 50 ns d. minimum clock high pulse width 50 ns e. minimum clock low pulse width 50 ns f. minimum setup clock rising edge to strobe 50 ns g. minimum strobe pulse width 50 ns h. minimum sleep to clock setup time 100 ns b lsb - d0 msb data clk stb a c d e f g sleepn h figure 4. serial port timing diagram
dual dmos full bridge motor driver with serial port control and dual regulators A3998 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com phase control this setting sets the relative states of the full-bridge outputs. this determines if the device operates in the forward or reverse (rela- tive) direction: serial port configuration bit (word 2) phase d2/d9 state outa outb 0 reverse low high 1 forward high low enable logic the enb1 and enb2 input terminals are provided for external pwm control of the two full bridges. when enbx is set to logic high, output on the corresponding full bridge is enabled. when set to logic low, the bridge output is chopped. fast decay time four bits (word 0/1, d10:d7) are available for each full bridge to set the fast decay portion, t fd , of the fixed off-time when inter- nal pwm control, mixed decay mode is selected. the fast decay portion is defined by: t fd = (1 + n ) t osc 8 ? t osc (4) where n is the word value, from 0 to 15. for example, given the internal oscillator frequency, f osc , of 4 mhz (typ) (t osc = 250 ns), the fixed off-time is adjustable from 2 to 32 s in increments of 2 s. for t fd > t off , the device effectively operates in fast decay mode. pwm blank timer when a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switch- ing transients related to distributed capacitance in the load. to prevent this current spike from erroneously resetting the source enable latch, the sense comparator is blanked. the programmable blanking function is enabled while the blank timer runs, which is after the off-time counter expires. when the enable (enbx) signal is chopped, or the phase setting in the the configuration register is changed, a pwm-off cycle is initiated and the blank timer is reset. blank time two bits (word 0/1, d1:d0) are available for each full bridge to set the current sense comparator blank time when any output driver is switched on. the settings are according to the following table (t osc is the period of the internal oscillator): serial port configuration bit (word 0/1) blank time d1 d0 0 0 4 t osc 0 1 6 t osc 1 0 12 t osc 1 1 24 t osc for example, given the internal oscillator frequency, f osc , of 4 mhz (typ) (t osc = 250 ns), the blank time is adjustable from 1 to 6 s. synchronous rectification when a pwm-off cycle is triggered, either by an enable chop command or an internal pwm control mode fixed off-time cycle, the load current recirculates according to the decay mode selected by the configuration register settings. after a short crossover delay, the synchronous rectification feature turns-on the appropriate mosfet (or pair of mosfets, for the mixed decay portion of the off-time) during the current decay and effectively shorts-out the body diodes with the low r ds(on) driver. this low- ers power dissipation significantly and can eliminate the require- ment for external schottky diodes. synchronous rectification can be configured in active mode or passive mode via the serial port (word 0/1, d11): ? active mode prevents reversal of load current by turning-off synchronous rectification when a zero current level is detected. ? passive mode allows reversal of current, but turns-off synchro- nous rectification if the load current inversion ramps up to the i trip current limit (see equation 1). sleepn pin active low input signal to reset serial port configu- ration register and enter standby mode. during standby mode, the regulators can still operate.
dual dmos full bridge motor driver with serial port control and dual regulators A3998 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com protection switching regulator the buck switch is disabled under the fol- lowing fault conditions: ? v bb < v bbuv(th) ? v cp < v bb + 5 v ? thermal shutdown fault thermal protection a thermal shutdown circuit turns-off all drivers and disables the switching regulator in the event of a fault due to excessive junction temperature. the serial port configura- tion register is not reset. shutdown occurs when the junction temperature reaches t jsd , 165c (typ). thermal shutdown has a hysteresis, t jsdhys , of approximately 20c (typ). the outputs of the device remain dis- abled until the fault condition is removed. pmon pin open drain output, logic high indicates v bb is above the uvlo threshold. undervoltage lockout at power-up, and in the event of low v in , the uvlo circuit disables the drivers and the serial port configuration register is reset to the default, por state. ocp when an overcurrent event is detected, the serial port configuration register is reset to the default (por) state. this fault is latched and can only be reset by cycling the power to the A3998 ( power-on reset, por) or by cycling standby mode (via the sleepn pin). note: an overcurrent fault event will not be generated during a shorted load condition if the blank time is programmed shorter than the t ocp . in this case, the overcurrent protection is still active, however, the internal current control circuit will operate as normal and terminate the source driver on-state upon completion of the blank time, before the ocp can trip the fault line and reset the serial port. power-on reset frst pin active high input signal forces reset (por). rstn pin an open drain output, rstn will be low if either of following conditions are true: ? v fb1 < v fbuv(th) ? frst high if neither of the conditions are true, there will be a 100 ms delay before rstn goes high. (see rst function with frst input timing diagram.)
dual dmos full bridge motor driver with serial port control and dual regulators A3998 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 1. configuration register bit map bit # function reset (por) value word 0 d0 bridge 1 blank time lsb 0 d1 bridge 1 blank time msb 0 d2 bridge 1 off time lsb 0 d3 bridge 1 off time bit 1 0 d4 bridge 1 off time bit 2 0 d5 bridge 1 off time bit 3 0 d6 bridge 1 off time msb 1 d7 bridge 1 fast decay lsb 0 d8 bridge 1 fast decay bit 1 0 d9 bridge 1 fast decay bit 2 0 d10 bridge 1 fast decay msb 0 d11 bridge 1 synchronous rectification control: 0 = active 1 = passive 0 d12 unused 0 d13 unused ? d14 word select 0 = 0 ? d15 word select 1 = 0 ? word 1 d0 bridge 2 blank time lsb 0 d1 bridge 2 blank time msb 0 d2 bridge 2 off time lsb 0 d3 bridge 2 off time bit 1 0 d4 bridge 2 off time bit 2 0 d5 bridge 2 off time bit 3 0 d6 bridge 2 off time msb 1 d7 bridge 2 fast decay lsb 0 d8 bridge 2 fast decay bit 1 0 d9 bridge 2 fast decay bit2 0 d10 bridge 2 fast decay msb 0 d11 bridge 2 synchronous rectification control: 0 = active 1 = passive 0 d12 unused 0 d13 unused ? d14 word select 0 = 1 ? d15 word select 1 = 0 ? continued on the next page?
dual dmos full bridge motor driver with serial port control and dual regulators A3998 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com word 2 d0 bridge 2 internal pwm mode: 0 = mixed decay mode 1 = slow decay mode 0 d1 bridge 2 external pwm mode (enb2 chopping): 0 = fast decay mode 1 = slow decay mode 0 d2 bridge 2 phase 0 d3 bridge 2 dac lsb (current ratio bit) 0 d4 bridge 2 dac bit 2 (current ratio bit) 0 d5 bridge 2 dac bit 3 (current ratio bit) 0 d6 bridge 2 dac bit 4 (current ratio bit) 0 d7 bridge 1 internal pwm mode: 0 = mixed decay mode 1 = slow decay mode 0 d8 bridge 1 external pwm mode (enb1 chopping): 0 = fast decay mode 1 = slow decay mode 0 d9 bridge 1 phase 0 d10 bridge 1 dac lsb (current ratio bit) 0 d11 bridge 1 dac bit 2 (current ratio bit) 0 d12 bridge 1 dac bit 3 (current ratio bit) 0 d13 bridge 1 dac bit 4 (current ratio bit) 0 d14 word select 0 = 0 ? d15 word select 1 = 1 ? table 1. configuration register bit map (continued) bit # function reset (por) value continued on the next page?
dual dmos full bridge motor driver with serial port control and dual regulators A3998 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com word 3 d0 thermal monitor: 0 = normal function 1 = rstn = thermal analog output, v = k t j 0 d1 charge pump: 0 = normal operation 1 = disable charge pump 0 d2 reserved for test 0 d3 reserved for test 0 d4 reserved for test 0 d5 reserved for test 0 d6 reserved for test 0 d7 reserved for test 0 d8 reserved for test 0 d9 reserved for test 0 d10 reserved for test 0 d11 reserved for test 0 d12 reserved for test 0 d13 reserved for test 0 d14 word select 0 = 1 ? d15 word select 1 = 1 ? table 1. configuration register bit map (continued) bit # function reset (por) value
dual dmos full bridge motor driver with serial port control and dual regulators A3998 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 2. current ratio configuration* dac bit 4 dac bit 3 dac bit 2 dac lsb current ratio (%) 1 1 1 1 100.0 1 1 1 0 95.65 1 1 0 1 91.30 1 1 0 0 86.95 1 0 1 1 82.61 1 0 1 0 78.26 1 0 0 1 73.91 1 0 0 0 69.56 0 1 1 1 60.87 0 1 1 0 52.17 0 1 0 1 43.48 0 1 0 0 34.78 0 0 1 1 26.08 0 0 1 0 17.39 0 0 0 1 0 0 0 0 0 disabled *internal pwm control mode selected
dual dmos full bridge motor driver with serial port control and dual regulators A3998 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pcb layout switcher the board layout has a significant impact on the performance of the device. it is important to isolate high current ground returns, in order to minimize ground bounce that could produce reference errors in the device. the method used to isolate power ground from noise sensitive circuitry is a star ground. this approach makes sure the high current components such as the input capaci- tor, output capacitor, and diode have very low impedance paths to each other. figure 5 illustrates the technique. the ground from each of the components should be very close to each other and be connected on the same surface as the components. internal ground planes should not be used for the star ground connec- tion, because vias add impedance to the current path. in order to further reduce noise effects on the pcb, noise sensitive traces should not be connected to internal ground planes. the feedback network from the switcher output should have an independent ground trace that goes directly to the exposed pad underneath the device. the exposed pad should be connected to internal ground planes and to any exposed copper used for heat dissipation. if the grounds from the device also are connected directly to the exposed pad, the ground reference from the feed- back network will be less susceptible to noise injection or ground bounce. to reduce radiated emissions from the high frequency switching nodes it is important to have an internal ground plane directly under the lx node. the plane should not be broken directly under the switching path because the lowest impedance path for radiated emissions is back to the star ground using the ground plane directly under the signal trace. if another trace does break the return path, the energy will have to find another path, which is through radiated emissions or through stray eddy currents. motor driver in order to use pwm current control, a low-value resistor is placed between the lssx pin and ground for current sensing purposes. to minimize ground-trace ir drops in sensing the output current level, the current sensing resistor should have an independent ground return to the star ground point. this trace should be as short as possible. for low-value sense resistors, the ir drops in the pcb can be significant, and should be taken into account. when selecting a value for the sense resistor be sure not to exceed the maximum voltage on the sensex pin of 500 mv at maximum load. during overcurrent events, this rating may be exceeded for short durations. thermal considerations the pcb should have a thick ground plane. for optimum electrical and thermal performance, the A3998 must be soldered directly onto the board. on the underside of the A3998 package is an exposed pad, which provides a path for enhanced thermal dis- sipation. the thermal pad must be soldered directly to an exposed surface on the pcb in order to achieve optimal thermal conduc- tion. thermal vias are used to transfer heat to other layers of the pcb. the load supply pin, vbb, should be decoupled with an electrolytic capacitor (typically 100 f) in parallel with a lower valued ceramic capacitor placed as close as practicable to the device switching regulator component selection external component recommended values are provided in table 3. v out1 the regulator requires an external clamping diode, d1, inductor, l1, and filter capacitor, cout1 (see figure 1). the output voltage is determined by an external resistive voltage divider, according to the following formula: v out1 = v fb1 (1 + r 1 / r 2) (5) application information star ground current path (on-cycle ) current path (off-cycle ) c in l q1 d c out r load figure 5. star ground connection
dual dmos full bridge motor driver with serial port control and dual regulators A3998 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pad A3998 gnd pmon rstn vref fb1 fb2 gd/vout2 vin out2b vbb out2a sense2 gnd sense1 out1a vbb csn vreg nc vcp cp2 cp1 sw1 out1b gnd frst sleepn clk data stb enb1 enb2 l1 d1 vbb cvbb1 cvbb2 rs2 rs1 vout2 cout2 cvreg ccp cvcp rcl2 r2 q1 r1 r4 r3 vout1 out1b out2b out1a out2a cout1 gnd pcb layout diagram pcb thermal vias trace (2 oz.) signal (1 oz.) ground (1 oz.) thermal (2 oz.) solder A3998 r1 r2 vout2 cout2 q1 l1 d1 cvbb2 rs1 rs2 rcl2 cvreg cvcp ccp cvbb1 cout1 gnd gnd gnd gnd gnd out2b out2a out1a out1b vbb r4 vout1 r3 u1
dual dmos full bridge motor driver with serial port control and dual regulators A3998 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the total resistance from v out1 to fb1 to gnd should be less than 10 k . d1 the schottky catch diode should be rated to handle 1.2 times the maximum load current. the voltage rating should be higher than the maximum input voltage expected during any operating condition. the duty cycle for high input voltages can be very close to 100%. l1 the inductor must be rated to handle the total load current and the value chosen must keep the ripple current to a reasonable value. the ripple current, i r , can be calculated by: i r = v l(off) (t off / l) (6) where v l(off) = v out1 + v f + i av r l (7) the switching frequency can then be estimated by: f pwm = 1 / ( t on + t off ) (8) where t on = i r l / v l(on) (9) and v l(on) = v bb ? i av r ds(on) ? i av r l ? v out1 (10) higher inductor values can be chosen to lower the ripple cur- rent. this may be an option if it is required to increase the total maximum current available that can be drawn from the switching regulator. the maximum total current available is: i load(max) = i cl (min) ? i r / 2 (11) where i cl (min) is from the electrical characteristics table. cout1 the output capacitor main consideration is voltage ripple on the output. for electrolytic output capacitors, a low esr type is recommended. the peak to peak output ripple is simply: i r(pp) = i r esr (12) note that the ripple current can be decreased by increasing the inductor value. the minimum voltage rating of the capacitor is 10 v, however, because esr decreases with voltage, the most cost effective choice may be a higher rated voltage. v out2 this output requires a 10 f ceramic output capacitor, cout2. table 3. recommended components configuration component output f pwm symbol description representative component v out1x 5 v / 1 a 220 khz l1 68 h 3bsumida rch1216bnp-680k cout1 220 f / 25 v, esr = 72 m rubycon zl 25zl220m8x11.5 d1 60 v / 3 a schottky diode nsq03a06 r1 2 k r2 499 3.3v/1a 230 khz l1 68 h 4bsumida rch1216bnp-680k cout1 220 f / 25 v, esr = 72 m rubycon zl 25zl220m8x11.5 d1 60 v / 3 a schottky diode vishay ss36 r1 2 k r2 866 v out2x q1 external mosfet - c gs < 1000 pf rsx sense resistor cout2 10 f /10 v x5r r3, r4
dual dmos full bridge motor driver with serial port control and dual regulators A3998 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package et, 32-pin qfn 32 32 2 1 2 1 a a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) concept drawing for reference only; not for tooling use (reference jedec mo-220vhhd-6) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 qfn50p500x500x100-33v6m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) b 32 2 1 pcb layout reference view 0.50 bsc 5.00 0.15 5.00 0.15 0.90 0.10 0.25 0.500.05 0.30 1 0.50 1.00 5.00 5.00 c 3.40 3.40 3.40 3.40 c 0.08 33x seating plane c d d coplanarity includes exposed thermal pad and terminals +0.05 ?0.07
dual dmos full bridge motor driver with serial port control and dual regulators A3998 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2011-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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